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MM74HC138 3-to-8 Line Decoder
September 1983 Revised February 1999
MM74HC138 3-to-8 Line Decoder
General Description
The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The MM74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder's outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
s Typical propagation delay: 20 ns s Wide power supply range: 2V-6V s Low quiescent current: 80 A maximum (74HC Series) s Low input current: 1 A maximum s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number MM74HC138M MM74HC138SJ MM74HC138MTC MM74HC138N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for DIP, SOIC, SOP and TSSOP
(c) 1999 Fairchild Semiconductor Corporation
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MM74HC138
Truth Table
Inputs Enable G1 X L H H H H H H H H G2 (Note 1) H X L L L L L L L L C X X L L L L H H H H Select B X X L L H H L L H H A X X L H L H L H L H Y0 H H L H H H H H H H Y1 H H H L H H H H H H Y2 H H H H L H H H H H Y3 H H H H H L H H H H Y4 H H H H H H L H H H Y5 H H H H H H H L H H Y6 H H H H H H H H L H Y7 H H H H H H H H H L Outputs
H = HIGH Level, L = LOW Level, X = don't care Note 1: G2 = G2A+G2B
Logic Diagram
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MM74HC138
Absolute Maximum Ratings(Note 2)
(Note 3) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin Power Dissipation (PD) (Note 4) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW (ICC) Storage Temperature Range (TSTG) - 0.5 to + 7.0V - 1.5 to VCC + 1.5V - 0.5 to VCC + 0.5V 20 mA 25 mA 50 mA - 65C to + 150C
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns -40 +85 C 2 0 Max 6 VCC Units V V
Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Note 4: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage
(Note 5)
Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8.0 TA = -40 to 85C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 Units V V V V V V V V V V V V V V V V A A
VIN = VIH or VIL | IOUT | 20 A 2.0V 4.5V 6.0V VIN = VIH or VIL |IOUT | 4.0 mA | IOUT | 5.2 mA 4.5V 6.0V 2.0V 4.5V 6.0V VIN = VIH or VIL | IOUT | 4.0 mA | IOUT | 5.2 mA 4.5V 6.0V 6.0V 6.0V
VOL
Maximum LOW Level Output Voltage
VIN = VIH or VIL | IOUT | 20 A
IIN ICC
Maximum Input Current Maximum Quiescent Supply Current
VIN = VCC or GND VIN = VCC or GND IOUT = 0 A
Note 5: For a power supply of 5V 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC138
AC Electrical Characteristics
VCC = 5V, TA = 25C, CL = 15 pF, tr = tf = 6 ns Symbol tPLH tPHL tPHL, tPLH tPHL Parameter Maximum Propagation Delay, Binary Select to any Output Maximum Propagation Delay, Binary Select to any Output Maximum Propagation Delay, G1 to any Output Maximum Propagation Delay G2A or G2B to Output tPLH Maximum Propagation Delay G2A or G2B to Output 18 25 ns 23 30 ns 18 25 ns 28 35 ns Conditions Typ 18 Guaranteed Limit 25 Units ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPLH Parameter Maximum Propagation Delay Binary Select to any Output LOW-to-HIGH tPHL Maximum Propagation Delay Binary Select to any Output HIGH-to-LOW tPHL, tPLH Maximum Propagation Delay G1 to any Output tPHL Maximum Propagation Delay G2A or G2B to Output tPLH Maximum Propagation Delay G2A or G2B to Output tTLH, tTHL Output Rise and Fall Time CIN CPD Maximum Input Capacitance Power Dissipation Capacitance
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + I CC.
Conditions
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V
TA= 25C Typ 75 15 13 100 20 17 75 15 13 82 28 22 75 15 13 30 8 7 3 30 26 200 40 34 150 30 26 175 35 30 150 30 26 75 15 13 10 150
TA= -40 to 85C Guaranteed Limits 189 38 32 252 50 43 189 38 32 221 44 37 189 38 32 95 19 16 10
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
(Note 6)
75
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MM74HC138
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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MM74HC138
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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MM74HC138 3-to-8 Line Decoder
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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